Method of manufacturing a semiconductor device
US11837645B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 21, 2022 |
| Grant date | Dec 5, 2023 |
| Priority date | — |
| Expiry date | Dec 21, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76814
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device including a substrate; a fin active region on the substrate and extending in a first direction; a gate structure extending across the fin active region and extending in a second direction; a source/drain region in the fin active region on a side of the gate structure; an insulating structure covering the gate structure and the source/drain region; and contact structures penetrating through the insulating structure and respectively connected to the source/drain region and the gate structure, wherein one of the contact structures includes a seed layer on the gate structure or the source/drain regions and including lower and upper regions, the lower region having a first grain size and the upper region being amorphous or having a grain size different from the first grain size, and a contact plug on an upper region of the seed layer and having a second grain size.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.