Wafer-level manufacturing process of a flexible integrated array sensor
US11839160B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 4, 2020 |
| Grant date | Dec 5, 2023 |
| Priority date | — |
| Expiry date | Jun 20, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N30/071
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
The present disclosure provides a flexible integrated array sensor and manufacturing methods thereof. The array sensor includes a silicon wafer, a readout circuit layer, a sensing array layer, and a polymer substrate layer disposed on the silicon wafer. The manufacturing method includes: preparing a silicon wafer; fabricating a plurality of function arrays, each including m*n function units, on a surface of the silicon wafer; etching one or more deep grooves on the surface of the silicon wafer between the arrays; fabricating a thinning support; and thinning a bottom surface of the silicon wafer to a target thickness so that the arrays are separated from each other. The etching depth for etching the one or more deep grooves is equal to or greater than the thickness of the silicon wafer after thinning.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.