Array substrate and display panel
US11841597B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 20, 2020 |
| Grant date | Dec 12, 2023 |
| Priority date | — |
| Expiry date | Oct 22, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02F1/13624
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
The present disclosure provides an array substrate and a display panel including the same. The array substrate includes a plurality of pixel units. Each of the pixel units includes a main pixel electrode, a sub-pixel electrode, a first thin film transistor (TFT) electrically connected to the sub-pixel electrode, a second TFT electrically connected to the first TFT, and a third TFT electrically connected to the main pixel electrode. The first TFT includes a first channel and a first semiconductor layer. The first channel includes two or more subchannels. The first semiconductor layer includes two or more semiconductor sublayers. Each of the semiconductor sublayers is disposed in a corresponding subchannel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.