Patent · US Active

Method and system for realizing FPGA server

US11841733B2 · kind B2 · utility

0Cited by
11References
8Claims
0Family size

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Key dates

Filing dateJan 8, 2020
Grant dateDec 12, 2023
Priority date
Expiry dateJan 8, 2040

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG06F15/78
  • WIPO fieldComputer technology
  • WIPO sectorElectrical engineering

Abstract

A method and system for realizing a FPGA server, wherein centralized monitoring and managing all SoC FPGA compute nodes within the server by a motherboard, the motherboard comprising: a plurality of self-defined management interfaces for connecting the SoC FPGA compute nodes to supply power and data switch to the SoC FPGA compute nodes; a management network switch module for interconnecting the SoC FPGA compute nodes and supplying management; and a core control unit for managing the SoC FPGA compute nodes through the self-defined management interfaces and a self-defined management interface protocol, and acquiring operating parameters of the SoC FPGA compute nodes to manage and monitor the SoC FPGA compute nodes based on the management interface protocol.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.