Method and system for tracing error of logic system design
US11841761B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 22, 2021 |
| Grant date | Dec 12, 2023 |
| Priority date | — |
| Expiry date | Feb 2, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/348
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for tracing an error of a logic system design includes obtaining an assertion failure of a combinational cone of the logic system design, the combinational cone including a plurality of sub-cones; and obtaining machine learning models of the sub-cones. Each sub-cone represents a sub-circuitry of the logic system design and has one or more input signals and an output signal. The assertion failure indicates an actual signal value of the combinational cone at a current clock cycle being different from an expected output value at the current clock cycle. The method also includes: performing backtracing on the sub-cones according to the assertion failure, the machine learning models of the sub-cones, and dynamic backtracing sensitivities corresponding to the sub-cones, to obtain a backtracing result; and outputting one or more target sub-cones as candidate root causes of the assertion failure according to the backtracing result.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.