Anti-fuse memory circuit
US11842766B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 10, 2022 |
| Grant date | Dec 12, 2023 |
| Priority date | — |
| Expiry date | Jun 9, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1066
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provided is an anti-fuse memory circuit. The anti-fuse memory circuit includes a memory array, a bit line (BL), and a word line (WL); an anti-fuse memory cell (FsBIn) electrically connected to the bit line (BL) through a first switch transistor (1Add); a second switch transistor (2Add) configured to connect the bit line (BL) to a transmission wire (100); a third switch transistor (3Add) configured to discharge the transmission wire (100); a reading module (102) including a first input end (+) connected to the transmission wire (100), a second input end (−) for receiving a reference voltage (VTRIP), and a sampling input end (C) for receiving a sampling signal (CLK); and a compensation module (101), connected to the third switch transistor (3Add) and configured to slow down a drop speed of a voltage at the transmission wire (100).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.