Devices including stacked nanosheet transistors
US11843001B2 · kind B2 · utility
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8References
13Claims
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Key dates
| Filing date | Jul 20, 2021 |
| Grant date | Dec 12, 2023 |
| Priority date | — |
| Expiry date | Oct 14, 2041 |
Classification
- Technology area (CPC B)Performing Operations; Transporting
- CPC primaryB82Y10/00
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
Nanosheet transistor devices are provided. A nanosheet transistor device includes a transistor stack that includes a lower nanosheet transistor having a first nanosheet width and a lower gate width. The transistor stack also includes an upper nanosheet transistor that is on the lower nanosheet transistor and that has a second nanosheet width and an upper gate width that are different from the first nanosheet width and the lower gate width, respectively. Related methods of forming a nanosheet transistor device are also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.