Gate etch back with reduced loading effect
US11843041B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 1, 2022 |
| Grant date | Dec 12, 2023 |
| Priority date | — |
| Expiry date | Jul 1, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/215
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes first and second gate structures over a substrate, the first gate structure has a first width that is smaller than a second width of the second gate structure, in which a lower portion of the first gate structure having a first work-function material (WFM) layer, the first WFM layer having a top surface, a lower portion of the second gate structure having a second WFM layer, the second WFM layer having a top surface. A first gate electrode is disposed over the first WFM layer and a second gate electrode has a lower portion disposed in the second WFM layer, in which the first gate electrode has a first width that is smaller than a second width of the second gate electrode, and wherein the top surface of the second WFM layer is at a level below a top surface of the second gate electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.