Switching device
US11843370B2 · kind B2 · utility
Assignees
Inventor
Key dates
| Filing date | Sep 8, 2022 |
| Grant date | Dec 12, 2023 |
| Priority date | — |
| Expiry date | Sep 8, 2042 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02B70/10
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A gate of the first p-type MOS transistor and the first and second control circuits are electrically coupled to a first node. The first control circuit lowers a voltage or the first node between a first time and a second time at which the first p-type MOS transistor is off. The second control circuit lowers the voltage of the first node between a third time and a fourth time at which the first p-type MOS transistor is on. The second time is later than the first time. The fourth time is later than the second and third times. The first p-type MOS transistor is turned on during a first period. A voltage decrease amount of the first node per unit time in the first control circuit is greater than that in the second control circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.