Method and system for enabling low-latency data communication by aggregating a plurality of network interfaces
US11843959B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 29, 2020 |
| Grant date | Dec 12, 2023 |
| Priority date | — |
| Expiry date | Aug 1, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04W28/0268
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The invention generally relates to a method and system for enabling low-latency data communication by aggregating a plurality of network interfaces, each network interface associated with a different network. The method and system measures in real-time, network performance capabilities associated with the networks via the respective network interfaces. The method and system then assigns two or more multi-threading processors in a multi-processor architecture configured to execute a plurality of threads for processing one or more data streams. The threading in each processor is interlinked with two or more network interfaces based on the measured network performance capabilities and network performance capability requirements of the one or more data streams, thereby enabling threading-based cooperation among multi-core processors in the multi-processor architecture and the plurality of network interfaces. The one or more data streams are then transmitted to the two or more network interfaces and thereon to the associated networks for transport.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.