Array substrate and display device
US11846856B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Mar 17, 2020 |
| Grant date | Dec 19, 2023 |
| Priority date | — |
| Expiry date | May 25, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/60
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
An array substrate has a plurality of sub-pixel regions. The array substrate includes a base substrate, gate lines disposed on a side of the base substrate and extending in a first direction, pixel electrodes each disposed in a respective one of the sub-pixel regions, and common electrodes disposed on a side, facing away from the base substrate, of the pixel electrodes and the gate lines. An orthographic projection of at least one common electrode on the base substrate at least partially overlaps with an orthographic projection of at least one gate line adjacent to the at least one common electrode on the base substrate, or a border of an orthographic projection of at least one common electrode on the base substrate partially overlaps with a border of an orthographic projection of at least one gate line adjacent to the at least one common electrode on the base substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.