Integrated circuit with debugger and arbitration interface
US11847006B2 · kind B2 · utility
1Cited by
5References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 31, 2020 |
| Grant date | Dec 19, 2023 |
| Priority date | — |
| Expiry date | May 2, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F21/85
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit includes: a debugger; and an interface coupled to the debugger. The interface has: arbitration logic coupled to the debugger; a power processor coupled to the arbitration logic; and a power management network coupled to the power processor. The integrated circuit also includes subsystems coupled to the interface. The debugger is configured to perform debugging operations of the subsystems via the interface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.