Device and method for high performance memory debug record generation and management
US11847037B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 16, 2020 |
| Grant date | Dec 19, 2023 |
| Priority date | — |
| Expiry date | Mar 13, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7201
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Example implementations include a method of receiving a host command identifier associated with a host command, determining a device command associated with the host command and a memory controller device, receiving a device command timestamp corresponding to a time of the determining the device command, and determining a debug record contemporaneously with the determining the device command, the debug record including the host command identifier, a device command identifier associated with the device command, and the device command timestamp. Example implementations also include a device operably coupled to a memory array, and with a memory controller device configured to receive a host command identifier associated with a host command, and configured to determine a device command associated with the host command and a memory controller device, and a debug record generator device operatively coupled to the memory controller device and configured to receive a device command timestamp corresponding to a time of the determined device command, and configured to determine a debug record contemporaneously with the determining the device command, the debug record including the host comma…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.