Data path interface circuit, memory and memory system
US11847073B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 31, 2021 |
| Grant date | Dec 19, 2023 |
| Priority date | — |
| Expiry date | Mar 5, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2254
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data path interface circuit includes: a writing path module, connected to an internal port and an external port and configured to transmit stored data to the internal port from the external port; a reading path module, connected to the internal port and external port respectively and configured to transmit the stored data to the external port from the internal port; a first delay module, connected to the external port and internal port respectively, and configured to obtain the stored data from the external port or internal port, perform delay processing on the stored data, and transmit the delayed stored data to the writing path module and/or reading path module; and a delay control module, connected to the first delay module and configured to receive a signal instruction from external and control delay time for the first delay module to perform the delay processing according to the signal instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.