Clearing register data using a write enable signal
US11847455B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 11, 2021 |
| Grant date | Dec 19, 2023 |
| Priority date | — |
| Expiry date | Jul 31, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C19/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing unit having a register file includes: a plurality of registers each having a write enable input configured to receive a write enable signal and a write data input connected to a write data path of the processing unit and configured to write data values from the write data path for storage in a register when the write enable signal is asserted; write circuitry configured in a normal mode of operation to assert the write enable signal of a respective one of the registers to cause operational data values to be written to that register from the write data path; and data cleansing circuitry configured to control a data cleansing mode in which write enable signals of all registers in the register file are simultaneously asserted to cause cleansing data values to be simultaneously written to all registers in the register file from the write data path.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.