Semiconductor chip including buried dielectric pattern at edge region, semiconductor package including the same, and method of fabricating the same
US11848285B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 15, 2022 |
| Grant date | Dec 19, 2023 |
| Priority date | — |
| Expiry date | Jun 9, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3512
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor chip, a semiconductor package including the same, and a method of fabricating the same, the semiconductor chip including a substrate that includes a device region and an edge region; a device layer and a wiring layer that are sequentially stacked on the substrate; a subsidiary pattern on the wiring layer on the edge region; a first capping layer that covers a sidewall of the subsidiary pattern, a top surface of the wiring layer, and a sidewall of the wiring layer, the first capping layer including an upper outer sidewall and a lower outer sidewall, the lower outer sidewall being offset from the upper outer sidewall; and a buried dielectric pattern in contact with the lower outer sidewall of the first capping layer and spaced apart from the upper outer sidewall of the first capping layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.