Semiconductor package
US11848307B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 17, 2021 |
| Grant date | Dec 19, 2023 |
| Priority date | — |
| Expiry date | Jun 8, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes a base substrate and an interposer substrate. The interposer substrate includes a semiconductor substrate, a first passivation layer, a wiring region, a through via penetrating through the semiconductor substrate and the first passivation layer, and a second passivation layer covering at least a portion of the first passivation layer and having an opening exposing a lower surface of the through via. The semiconductor package further includes a conductive pillar extending from the opening of the second passivation layer; and a conductive bump disposed between the conductive pillar and the base substrate. The opening of the second passivation layer has inclined side surfaces such that a width of the opening decreases towards the first passivation layer, and side surfaces of the conductive pillar are positioned to overlap the inclined side surfaces of the second passivation layer in a vertical direction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.