Majority voter with error detection
US11848673B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 16, 2023 |
| Grant date | Dec 19, 2023 |
| Priority date | — |
| Expiry date | Aug 16, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00392
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated circuit for use in high-reliability electronic systems contains one or more digital majority voters with corresponding disagreement detectors connected to the same input signals producing a majority value output and an error signal that is active when not all input signals agree. Internal error signals from multiple majority voter/disagreement detectors as well as external error inputs may be combined using disjunctive error logic to produce an “error detected” output indication. Cold-sparing and hot-plugging are supported by providing cold-sparable electrostatic discharge protection circuits and power-on reset circuitry controlling cold-sparable output stages. Internal modular redundancy provides immunity to single-event transients as well as enhanced reliability. Redundant electronic systems using the majority voter with error detection are also provided, as are fault notification systems that use the disjunctive error logic and external error input feedthrough capabilities of serially-connected integrated circuits to produce an error indication for a plurality of subsystems.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.