Method and apparatus for compression multiplexing for sparse computations
US11848689B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 4, 2022 |
| Grant date | Dec 19, 2023 |
| Priority date | — |
| Expiry date | Mar 4, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/0495
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present disclosure include a digital circuit and method for compressing input digital values. A plurality of input digital values may include zero values and non-zero values. The input digital values are received on M inputs of a first switching stage. The first switching stage is arranged in groups that rearrange the non-zero values on first switching stage outputs according to a compression and shift. The compression and shift position the non-zero values on outputs coupled to inputs of a second switching stage. The second switching stage consecutively couples non-zero values to N outputs, where N is less than M.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.