System and method of clock recovery with low phase-error for card emulation clock-less NFC transceivers
US11849018B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 11, 2022 |
| Grant date | Dec 19, 2023 |
| Priority date | — |
| Expiry date | May 11, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/046
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Disclosed is a card clock recovery system for use in an NFC card transceiver couplable to an NFC reader. The card clock recovery system has: a phase lock loop having: a phase/frequency detector, which is configured to receive a reference signal provided at an RX port of a matching network during a receiving mode of the NFC transceiver or to receive a reference signal provided at the RX port of the matching network during a transmission mode of the NFC transceiver, to receive a loop feedback signal, and to provide a phase error signal that represents a phase difference between the reference signal and the loop feedback signal; a loop filter configured to receive a corrected phase error signal that is derived from the phase error signal, and to provide a filtered corrected phase error signal; a controllable oscillator, which is configured to receive the filtered corrected phase error signal and to provide a controlled frequency output signal, which is provided as the card clock generation control signal to a card clock generation unit of an NFC card transceiver, and as the loop feedback signal, via the loop feedback line, to the phase/frequency detector. The card clock recovery syste…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.