Low latency video codec and transmission with parallel processing
US11849130B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 29, 2022 |
| Grant date | Dec 19, 2023 |
| Priority date | — |
| Expiry date | Apr 29, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N19/176
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Methods and devices for a parallel multi-processor encoder system for encoding video data. The video data comprises a sequence of frames, wherein each frame comprises a plurality of blocks of pixels in sequential rows. For each frame, the system divides the plurality of blocks into a plurality of subsets of blocks, wherein each subset of blocks is allocated to a respective processor of the parallel multi-processor system. Each respective processor of the parallel multi-processor system may sequentially encode rows of the subset of blocks allocated to the respective processor and sequentially transmit each encoded row of blocks as a bit stream to a decoder on a channel. For each row, the respective encoded row of blocks is transmitted to the decoder for each processor prior to transmission of the next sequential respective encoded row of blocks for any processor. Additionally, a similar parallel multi-processor decoder system is described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.