Address fault detection system
US11853157B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 17, 2021 |
| Grant date | Dec 26, 2023 |
| Priority date | — |
| Expiry date | Mar 25, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0409
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An address fault detection system includes write and read access circuits and a fault management circuit. The write access circuit receives an address and reference data for a write operation associated with a memory and parity data generated based on the reference data, and writes the reference data and the parity data to first and second memory blocks of the memory, respectively. The read access circuit receives the same address for a read operation associated with the memory and reads another reference data and another parity data from the first and second memory blocks, respectively. The fault management circuit compares the read parity data with parity data generated based on the read reference data to detect an address fault in the memory. The written and read reference data are different when the address fault is detected, and same when the address fault is not detected.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.