Patent · US Active

Semi and cached TLP coalescing

US11853218B2 · kind B2 · utility

0Cited by

8References

20Claims

0Family size

Assignee

Western Digital Technologies, Inc. · US

Inventors

Amir Segev · Even Yehuda, IL
Amir Rozen · Rishon LeZion, IL
Shay Benisty · Beer Sheva, IL

Key dates

Filing date	May 18, 2022
Grant date	Dec 26, 2023
Priority date	—
Expiry date	Aug 10, 2042

Classification

Technology area (CPC G)Physics
CPC primaryG06F2212/7203
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive a command, wherein the command comprises a plurality of logical block addresses (LBAs), determine that one or more LBAs of the plurality of LBAs are not aligned to a transfer layer packet (TLP) boundary, determine whether the one or more LBAs that are not aligned to a TLP boundary has a head that is unaligned that matches a previously stored tail that is unaligned, and merge and transfer the head that is unaligned with a previously stored tail that is unaligned when the head that is unaligned matches the previously stored tail that is unaligned.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.