Partial-address-translation-invalidation request
US11853228B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 10, 2022 |
| Grant date | Dec 26, 2023 |
| Priority date | — |
| Expiry date | Jun 10, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/683
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Partial-address-translation-invalidation request to cause cache control circuitry to: identify whether a given cache entry of the address translation cache is a target cache entry to be invalidated, wherein the target cache entry comprises a cache entry for which the address translation data comprises partial address translation data indicative of an address of the next level page table specified by a table address of a target page table entry when used as the branch page table entry; and trigger an invalidation of the given cache entry when the given cache entry is identified to be the target cache entry. The given cache entry is permitted to be retained when the given cache entry provides full address translation data indicative of an address of a corresponding region of address space corresponding to an output address specified by the target page table entry when used as the leaf page table entry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.