Hardware accelerator circuits for near storage compute systems
US11853239B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 11, 2022 |
| Grant date | Dec 26, 2023 |
| Priority date | — |
| Expiry date | Apr 11, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1689
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus is provided that includes a memory system that includes a memory controller coupled to a storage device capable of streaming data at a first data rate. The memory controller is configured to read a first amount of input data from the storage device at an input data rate equals the first data rate, and provide the first amount of input data at the input data rate to a hardware circuit. The hardware circuit is configured to filter the first amount of input data to provide a second amount of output data at an output data rate, the second amount of output data less than the first amount of input data, the output data rate less than the input data rate. The hardware circuit filters the first amount of input data without repeatedly moving data back and forth between the storage device, a memory buffer, and the hardware circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.