Data transmission circuit, data transmission method, and memory
US11853240B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 8, 2022 |
| Grant date | Dec 26, 2023 |
| Priority date | — |
| Expiry date | Jul 29, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1016
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The data transmission circuit includes: at least two data transmission structures. Each data transmission structure includes a memory transmission terminal, a bus transmission terminal, and an interactive transmission terminal. Data inputted from the memory transmission terminal is outputted through the bus transmission terminal or the interactive transmission terminal. Data inputted from the bus transmission terminal is outputted through the memory transmission terminal or the interactive transmission terminal. Data inputted from the interactive transmission terminal is outputted through the bus transmission terminal or the memory transmission terminal. A control module receives an input control signal and an adjustment control signal that are provided by the memory; the control module is configured to output the input control signal in a delayed manner based on the adjustment control signal, so as to generate an output control signal corresponding to the input control signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.