Methods and systems for integrated circuit photomask patterning
US11853674B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 27, 2022 |
| Grant date | Dec 26, 2023 |
| Priority date | — |
| Expiry date | Mar 7, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2117/06
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
Methods and systems for IC photomask patterning are described. In some embodiments, a method includes inserting a dummy region in an IC design layout, the IC design layout includes an active region, and the active region and the dummy region is separated by a first distance. The method further includes performing one or more operations on the IC design layout, and the active region and the dummy region is separated by a second distance substantially less than the first distance. The method further includes performing a dummy region size reduction on the IC design layout to increase the second distance to a third distance substantially greater than the second distance, and the third distance is substantially greater than a minimum feature size to be patterned by a photolithography tool. The method further includes forming a photomask using the IC design layout.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.