Gate driver including dummy output buffer and display device including same
US11854467B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 17, 2021 |
| Grant date | Dec 26, 2023 |
| Priority date | — |
| Expiry date | Nov 17, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2320/0295
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A gate driver and a display device including the gate driver are discussed. The gate driver in one example includes a shift register configured to control charging and discharging of a Q node and a QB node, and i output buffers sequentially connected to the shift register, where i is a natural number of at least 2. Each output buffer is configured to output a gate signal to a corresponding gate line in response to a voltage of the Q node and a voltage of the QB node. The gate driver further includes a dummy output buffer connected to the last stage of the shift register and configured to output a dummy signal to a dummy line in response to the voltage of the Q node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.