State detection circuit for anti-fuse memory cell, and memory
US11854605B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 7, 2022 |
| Grant date | Dec 26, 2023 |
| Priority date | — |
| Expiry date | Jun 24, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B20/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A state detection circuit for an anti-fuse memory cell includes: amplifier, having first input terminal connected with first reference voltage, second input terminal connected with first node and output terminal connected with second node; anti-fuse memory cell array, including anti-fuse memory cell sub-arrays, bit lines of sub-arrays are connected with first node, word lines of sub-arrays are connected with controller and each sub-array includes anti-fuse memory cells; first switch element, having first terminal connected with power supply, second terminal connected with first node and control terminal connected with second node; second switch element, having first terminal connected with power supply, second terminal connected with third node and control terminal connected with second node; third switch element, having first terminal connected with third node, grounded second terminal and control terminal connected with controller; and comparator, having first and second input terminals connected with third node and second reference voltage respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.