Anti-fuse memory cell state detection circuit and memory
US11854633B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 27, 2021 |
| Grant date | Dec 26, 2023 |
| Priority date | — |
| Expiry date | Feb 26, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/068
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A state detection circuit of an anti-fuse memory cell includes a first switching element, having a first end connected to a power supply, a second end connected to a first node, and a control end connected to a controller; an anti-fuse memory cell array including a plurality of anti-fuse memory cell sub-arrays, bit lines of the plurality of anti-fuse memory cell sub-arrays being all connected to the first node, and word lines of the plurality of anti-fuse memory cell sub-arrays being all connected to the controller; and a comparator, having a first input end connected to the first node, and a second input end connected to a reference voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.