Signal masking circuit and semiconductor memory
US11854653B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 14, 2022 |
| Grant date | Dec 26, 2023 |
| Priority date | — |
| Expiry date | Apr 14, 2042 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A signal masking circuit includes a receiving circuit, a delay control circuit, and a logical operation circuit. The receiving circuit is configured to: receive a signal to be processed and a chip select (CS) signal, and output an initial processing signal and an initial CS signal. The delay control circuit is configured to perform delay and logical control operations on the initial CS signal to obtain a CS masking signal, where a pulse width of the CS masking signal is greater than or equal to two preset clock periods. The logical operation circuit is configured to perform invalid masking on the initial processing signal according to the CS masking signal to obtain a target signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.