Semiconductor structure and manufacturing method thereof

US11854862B2 · kind B2 · utility

Assignee

• CHANGXIN MEMORY TECHNOLOGIES, INC. · CN

Inventors

• Guangsu SHAO · Hefei, CN
• Deyuan Xiao · Shanghai, CN
• Yunsong QIU · Hefei, CN
• Youming Liu · Longbeilingcun, CN
• Yi Jiang · Hefei, CN
• Xingsong SU · Hefei, CN
• Yuhan Zhu · Hefei, CN

Key dates

• Filing date: Jun 27, 2022
• Grant date: Dec 26, 2023
• Expiry date: Jun 27, 2042

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/482
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

The present disclosure relates to a semiconductor structure and a manufacturing method thereof. The method of manufacturing a semiconductor structure includes: providing a base; forming a plurality of first trenches arranged in parallel at intervals and extending along a first direction, and an initial active region between two adjacent ones of the first trenches, wherein the initial active region includes a first initial source-drain region close to a bottom of the first trench, a second initial source-drain region away from the bottom of the first trench, and an initial channel region located between the first initial source-drain region and the second initial source-drain region; forming a protective dielectric layer, wherein the protective dielectric layer covers a sidewall of the second initial source-drain region and a sidewall of the initial channel region; thinning the first initial source-drain region.