Method for forming titanium nitride barrier with small surface grains in interconnects
US11854980B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 3, 2020 |
| Grant date | Dec 26, 2023 |
| Priority date | — |
| Expiry date | Dec 31, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/5226
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a semiconductor device, comprising: forming a first conductive layer on an active device of a substrate; forming a dielectric layer on the first conductive layer; forming a through hole passing through the dielectric layer to expose a portion of the first conductive layer; conformally depositing a glue layer in the through hole to cover the portion of the first conductive layer comprising: forming a plurality of isolated lattices in an amorphous region at which the isolated lattices are uniformly distributed and extend from a top surface of the glue layer and terminate prior to reach a bottom of the glue layer, wherein the glue layer has a predetermined thickness; depositing a conductive material on the glue layer within the through hole, thereby forming a contact via; and forming a second conductive layer on the contact via over the first conductive layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.