Display device having power line electrically connected to electrode layers located above and below transistor
US11855104B2 · kind B2 · utility
0Cited by
7References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 16, 2020 |
| Grant date | Dec 26, 2023 |
| Priority date | — |
| Expiry date | Nov 16, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2320/0242
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A display device includes: a first electrode layer; a semiconductor layer including a source region, a drain region, and a channel region, wherein at least a portion of the source region or the drain region overlaps the first electrode layer; a second electrode layer arranged adjacent to the channel region; a third electrode layer overlapping the second electrode layer and at least a portion of the source region or the drain region; and a power line electrically connected to the first electrode layer and the third electrode layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.