Power semiconductor device

US11855203B2 · kind B2 · utility

Assignee

• University of Electronic Science and Technology of China · CN

Inventors

• Ming Qiao · Chengdu, CN
• Liu Yuan · Ningbo City, CN
• Zhao Wang · Tangxia, CN
• Wenliang Liu · Beijing, CN
• Bo Zhang · Shanghai, CN

Key dates

• Filing date: Jul 5, 2021
• Grant date: Dec 26, 2023
• Expiry date: Dec 29, 2041

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/116

Abstract

A power semiconductor device includes a P-type substrate, an N-type well region, a P-type body region, a gate oxide layer, a polysilicon gate, a first oxide layer, a first N+ contact region, a first P+ contact region, drain metal, a first-type doped region, and a gate oxide layer. An end of the P-type body region is flush with or exceeds an end of the polysilicon gate, wherein Cgd of the power semiconductor device is reduced and a switching frequency of the power semiconductor device is increased. A polysilicon field plate connected with a source is introduced over a drift region that is not only shield an influence of the polysilicon gate on the drift region, thereby eliminating Cgd caused by overlapping of traditional polysilicon gate and drift region, but also enable the power semiconductor device to have strong robustness against an hot carrier effect.