Floating high-voltage level translator with adaptive bypass circuit
US11855630B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 31, 2022 |
| Grant date | Dec 26, 2023 |
| Priority date | — |
| Expiry date | May 31, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/017509
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Techniques are described herein to enhance capability of floating level translators. For example, increased headroom is accomplished by adaptively bypassing the protection elements of the voltage level translator. In an example, a floating level translator can translate an input signal from a low-voltage domain to a high-voltage domain. A bypass circuit is coupled across the protection elements. The bypass circuit selectively engages during low-voltage operation (e.g., thereby providing a lower loss path relative to loss caused by the high-voltage protection elements and thus increasing the headroom swing), and disengages responsive to the high-voltage reference rail of the high-voltage domain exceeding a threshold or otherwise being high enough (e.g., greater than the potential of the low-voltage domain power rail). The bypass circuit can be implemented in a relatively low-complexity manner (e.g., back-to-back high-voltage FETs) without additional signals to control low-voltage capability.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.