Patent · US Active

Defense of JTAG I/O network

US11856096B2 · kind B2 · utility

0Cited by

0References

19Claims

0Family size

Assignee

University of Florida Research Foundation, INC. · US

Inventors

Swarup Bhunia · Gainesville, US
Christopher Vega · Gainesville, US
Shubhra Deb Paul · Gainesville, US
Parker Difuntorum · Gainesville, US
Reiner Dizon · Gainesville, US
Patanjali Sristi Lakshmiprasanna Sriramakumara · Gainesville, US

Key dates

Filing date	Jun 3, 2021
Grant date	Dec 26, 2023
Priority date	—
Expiry date	Jun 3, 2041

Classification

Technology area (CPC H)Electricity
CPC primaryH04L2209/12
WIPO fieldDigital communication
WIPO sectorElectrical engineering

Abstract

An integrated circuit includes, in part, a key management unit configured to generate a seeding key during a start-up phase, an encryption module configured to encrypt data using the seeding key and deliver the encrypted data to a second integrated circuit, and an encoder configured to encode the seeding key and deliver the encoded seeding key to the second IC. The second integrated circuit includes, in part, a decoder configured to decode the seeding key. Each of the integrated circuits further includes, in part, a linear-feedback shift register that receives the same clock signals and loads the seeding key.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.