Semiconductor memory device with selection patterns, storage patterns, and a gap fill layer and method for fabricating the same
US11856794B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2021 |
| Grant date | Dec 26, 2023 |
| Priority date | — |
| Expiry date | Oct 15, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8825
Abstract
A semiconductor memory device includes a first memory cell provided on a substrate, a second memory cell provided on the substrate and spaced apart from the first memory cell, a passivation layer extending along a side surface of the first memory cell and a side surface of the second memory cell, and a gap fill layer covering the passivation layer. Each of the first memory cell and the second memory cell includes a selection pattern having ovonic threshold switching characteristics, and a storage pattern provided on the selection pattern. The passivation layer includes a lower portion filling a space between the selection pattern of the first memory cell and the selection pattern of the second memory cell, and an upper portion extending along a side surface of the storage pattern of each of the first memory cell and the second memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.