Low-dropout voltage regulator
US11860656B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 9, 2022 |
| Grant date | Jan 2, 2024 |
| Priority date | — |
| Expiry date | Jul 2, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F3/45183
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A low-dropout voltage regulator is provided. The low-dropout voltage regulator includes a differential amplifier pair, a secondary amplification circuit that is self-stabilized, an output circuit, and a frequency compensation circuit. The secondary amplification circuit includes a first amplification transistor and a second amplification transistor. The first amplification transistor includes a first terminal, a second terminal, and a third terminal. The second amplification transistor includes a first terminal, a second terminal, and a third terminal. The second terminal of the first amplification transistor is electrically connected to the second terminal of the second amplification transistor to form an input terminal of the secondary amplification circuit to be connected to an output terminal of the differential amplifier pair. The frequency compensation circuit is disposed between an output terminal of the secondary amplification circuit, a second terminal of an output transistor, and a third terminal of the output transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.