Low-overhead, bidirectional error checking for a serial peripheral interface
US11860730B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 6, 2021 |
| Grant date | Jan 2, 2024 |
| Priority date | — |
| Expiry date | Mar 11, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4291
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Example embodiments relate to low-overhead, bidirectional error checking for a serial peripheral interface. An example device includes an integrated circuit. The device also includes a serial peripheral interface (SPI) with a Master In Slave Out (MISO) channel and a Master Out Slave In (MOSI) channel. The MOSI channel is configured to receive a write address, payload data, and a forward error-checking code usable to identify data corruption within the write address or the payload data. The integrated circuit is configured to calculate and provide a reverse error-checking code usable to identify data corruption within the write address or the payload data. Additionally, the integrated circuit is configured to compare the forward error-checking code to the reverse error-checking code. Further, the integrated circuit is configured to write, to the write address if the forward error-checking code matches the reverse error-checking code, the payload data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.