Semiconductor memory devices and memory systems
US11860734B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 4, 2022 |
| Grant date | Jan 2, 2024 |
| Priority date | — |
| Expiry date | May 4, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/3715
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a memory cell array, an on-die error correction code (ECC) engine, and a control logic circuit. The on-die ECC engine, based on an ECC, in a write operation, performs an ECC encoding on main data to generate first parity data, selectively replaces a portion of the first parity data with a poison flag to generate second parity data based on a poison mode signal, provides the main data to a normal cell region in a target page of the memory cell array, and provides the first parity data to a parity cell region in the target page or provides the poison flag and the second parity data to the parity cell region. The control logic circuit controls the on-die ECC engine and generates the poison mode signal, based on a command and an address from a memory controller.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.