Method and apparatus for performing power stress test on FPGA acceleration card, and storage medium
US11860747B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 27, 2021 |
| Grant date | Jan 2, 2024 |
| Priority date | — |
| Expiry date | Aug 8, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for performing a power stress test on an FPGA acceleration card and a computer-readable storage medium. The method includes: dividing, according to a partial reconfiguration method, a hardware resource of an FPGA acceleration card into a static region serving as a hardware logic implementation region for performing a normal function test, and a dynamic PR region including a blank mode occupying no hardware resource and a power test mode for performing a power stress test, and burning FPGA firmware having a partial reconfiguration function to a flash memory; upon receiving a request for power stress test, configuring an operation mode of the dynamic PR region to be the power test mode, loading, to the dynamic PR region, a dynamic PR configuration file burned in the flash memory; and calling a power stress test module to execute the power stress test in the dynamic PR region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.