Patent · US Active

Reduced simulation verification complexity of cache purge

US11860789B2 · kind B2 · utility

1Cited by

2References

18Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Yvo Thomas Bernard Mulder · Reutlingen, DE
Ralf Ludewig · Schenefeld, DE
Huiyuan Xing · Schwieberdingen, DE
Ulrich Mayer · Weißenhorn, DE

Key dates

Filing date	Mar 21, 2022
Grant date	Jan 2, 2024
Priority date	—
Expiry date	Jun 17, 2042

Classification

Technology area (CPC G)Physics
CPC primaryG06F2212/601
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A cache purge simulation system includes a device under test with a cache skip switch. A first cache skip switch includes a configurable state register to indicate whether all of an associated cache is purged upon receipt of a cache purge instruction from a verification system or whether a physical partition that is smaller than the associated cache is purged upon receipt of the cache purge instruction from the verification system. A second cache skip switch includes a configurable start address register comprising a start address that indicates a beginning storage location of a physical partition of an associated cache and a configurable stop address register comprising a stop address that indicates a ending storage location of the physical partition of the associated cache.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.