Techniques for tamper detection and protection of a memory module
US11861053B2 · kind B2 · utility
0Cited by
2References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 16, 2020 |
| Grant date | Jan 2, 2024 |
| Priority date | — |
| Expiry date | Dec 26, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2221/2143
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques for tamper detection of a memory module having non-volatile memory devices resident on a printed circuit board (PCB) by circuitry of a controller also resident on the PCB. Examples include determining resistance values of a character pattern sprayed on a side of a cover facing the non-volatile memory devices using conductive ink following first and second boots of the memory module and asserting a bit of a register to indicate tampering of the memory modules based on a comparison of the resistance values. Tamper policy actions may be initiated based on detection of tampering.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.