TLC data programming with hybrid parity
US11861195B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 15, 2021 |
| Grant date | Jan 2, 2024 |
| Priority date | — |
| Expiry date | Feb 18, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1004
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure generally relates to improving programming to data storage devices, such as solid state drives (SSDs). A first memory device has a first XOR element and a second memory device has a second XOR element. The ratio of the first XOR element to the capacity of the first memory device is substantially smaller than the ratio of the second XOR element to the capacity of the second memory device. A read verify operation to find program failures is executed on either a wordline to wordline basis, an erase block to erase block basis, or both a wordline to wordline basis and an erase block to erase block basis. Because the program failures are found and fixed prior to programming to the second memory device, the second XOR element may be decreased substantially.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.