Memory device
US11862220B2 · kind B2 · utility
0Cited by
11References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 9, 2022 |
| Grant date | Jan 2, 2024 |
| Priority date | — |
| Expiry date | Jun 9, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B51/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provided is a memory device. The memory device may include a substrate, a ferroelectric field effect transistor disposed on the substrate, a first channel contacting a gate structure of the ferroelectric field effect transistor and extending in a vertical direction from the gate structure of the ferroelectric field effect transistor, a selection word line disposed at one side of the first channel, a first gate dielectric layer disposed between the first channel and the selection word line, and a cell word line disposed on top of the first channel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.