Bit line sense circuit and memory
US11862239B2 · kind B2 · utility
0Cited by
22References
18Claims
0Family size
Assignee
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Key dates
| Filing date | Sep 16, 2021 |
| Grant date | Jan 2, 2024 |
| Priority date | — |
| Expiry date | May 18, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/005
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A bit line sense circuit and a memory are disclosed in the present application. The bit line sense circuit includes: L storage unit groups, each storage unit group including H bit lines, both L and H being positive integers greater than or equal to 2; and M sense amplifier groups, configured to write or read storage data to or from the bit lines in the storage unit groups and electrically connected to the L storage unit groups, M being an integer multiple of L or L being an integer multiple of M. Two adjacent bit lines of the H bit lines are connected to the different sense amplifier groups.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.