Memory circuit and method of operating same
US11862264B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 18, 2023 |
| Grant date | Jan 2, 2024 |
| Priority date | — |
| Expiry date | Jan 18, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory circuit includes a sense amplifier coupled to a non-volatile memory cell, and a detection circuit coupled to the sense amplifier and the non-volatile memory cell. The sense amplifier includes a comparator. The comparator includes a first input terminal coupled to the non-volatile memory cell by a first node, and configured to receive a first voltage, a second input terminal configured to receive a second voltage, and a first output terminal configured to output a first output signal. The detection circuit is configured to latch the first output signal and disrupt a current path between the non-volatile memory cell and the sense amplifier. The detection circuit includes a first inverter. A first input terminal of the first inverter is configured to receive the first output signal. A first output terminal of the first inverter is configured to generate an inverted first output signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.