Patent · US Active

Memory test systems and memory test methods

US11862278B2 · kind B2 · utility

0Cited by

6References

14Claims

0Family size

Assignee

CHANGXIN MEMORY TECHNOLOGIES, INC. · CN

Inventors

Hao He · Shanghai, CN
Dan Tho Lu · Minden, US
Yang Wang · Suzhou, CN

Key dates

Filing date	Mar 12, 2021
Grant date	Jan 2, 2024
Priority date	—
Expiry date	Oct 9, 2041

Classification

Technology area (CPC G)Physics
CPC primaryG11C2029/5602
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

The present disclosure relates to a memory test system and a memory test method. The memory test system comprises: a plurality of test devices, a host computer, and driving modules. Each of the test devices is provided with a test interface used for connecting a memory to be tested. The host computer is respectively connected to the plurality of test devices and configured to control the test devices to test the memory to be tested. The driving modules are connected to the test devices and configured to output, to the test devices, driving signals used for driving the test devices to perform data interaction with the host computer.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.