Sum address memory decoded dual-read select register file
US11862289B2 · kind B2 · utility
0Cited by
3References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 11, 2021 |
| Grant date | Jan 2, 2024 |
| Priority date | — |
| Expiry date | Jun 28, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Aspects of the invention include decoding a base address and an offset to generate a first potential memory address and a second potential memory address. A first cell data associated with the first potential memory address of a first partitioned array and a second cell data associated with a second partitioned array are evaluated. Carry-out bit information is received from a summing operation of the base address and the offset, the operating being performed in parallel to the decoding. The carry-out bit information is used to select either the first cell data or the second cell data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.